Decoupling Capacitor Calculator
Design your power distribution network (PDN) by calculating decoupling capacitor values, ESR/ESL effects, and multi-layer capacitor strategies for noise-free IC power supplies.
Multi-Layer Capacitor Strategy
Bulk capacitors (10–100 µF, ESR 0.05–0.5 Ω): Energy storage, low-frequency filtering (10 Hz–10 kHz). Place 1–2 near each IC cluster.
Ceramic capacitors (0.1–10 µF, ESR <10 mΩ): High-frequency transient response (10 kHz–100 MHz). Place multiple (1 per 4–8 outputs) directly adjacent to IC pins with short vias.
Reference: Capacitor Selection by IC Type
| IC Type | Bulk Cap | Ceramic Cap | Ratio |
|---|---|---|---|
| Microcontroller (8-bit) | 10 µF | 1–2 × 0.1 µF | 1:1 |
| FPGA (low-mid density) | 47–100 µF | 5–10 × 0.1 µF | 1:2 |
| FPGA (high density) | 100–220 µF | 10–20 × 0.1 µF | 1:3+ |
| High-speed DSP | 47–100 µF | 8–15 × 0.1 µF | 1:2 |
Why Multi-Layer Matters
A single capacitor value cannot handle the full frequency spectrum. Bulk capacitors store energy but respond slowly (milliseconds). Ceramic capacitors respond fast (nanoseconds) but store little energy. Using both layers keeps impedance low across 6+ decades of frequency, preventing voltage droop and ringing.
The impedance "valley" between bulk and ceramic layers is called the impedance minimum zone (IMZ). This is where the PDN performs best. Poor placement or missing capacitor values create impedance peaks that cause noise coupling to adjacent signals.
Frequently Asked Questions
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A decoupling capacitor is a capacitor connected between the power supply (VCC) and ground of an integrated circuit to reduce voltage noise and transient voltage spikes. It supplies charge to the IC during sudden current changes and filters out high-frequency noise caused by switching circuits.
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Digital ICs draw current in fast bursts during logic transitions. Without decoupling capacitors, this creates voltage dips on the power rail that can cause logic errors, metastability, or reduced circuit speed. Decoupling capacitors stabilize the local voltage near the IC.
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Bulk capacitors (typically 10–100 µF electrolytic) have high capacitance but high ESR and ESL, filtering low-frequency noise. Ceramic capacitors (typically 0.1–10 µF) have lower ESR/ESL and respond faster to high-frequency transients. A good PDN uses both layers.
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Total capacitance depends on tolerable voltage ripple, transient current magnitude, and supply voltage. Rule of thumb: C = ΔI × Δt ÷ ΔV, where ΔI is current change, Δt is time window, ΔV is acceptable voltage dip. Typical designs use 0.1 µF per digital output.
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ESR (Equivalent Series Resistance) is the internal resistance of the capacitor. During transient current surges, ESR causes additional voltage drop: ΔV = I_transient × ESR. Ceramic capacitors have much lower ESR (mΩ) than electrolytics (Ω), making them critical for fast noise suppression.
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ESL (Equivalent Series Inductance) is the parasitic inductance of the capacitor leads and layout. At high frequencies, impedance rises due to ESL. Using short traces, via placement near the capacitor pad, and multiple capacitors in parallel all reduce effective ESL.
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The number depends on the IC datasheet recommendations, supply current, and acceptable voltage ripple. A common starting point: use one 0.1 µF ceramic capacitor for every 4–8 digital outputs (or per IC datasheet), plus bulk capacitors (10–100 µF per IC).
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Place capacitors as close as possible to the IC power pins, using short, wide traces to minimize loop inductance. Use multiple vias near pads for both the capacitor and IC pins. Group capacitors by value (smallest ceramics nearest the IC, larger bulk capacitors slightly farther).
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A PDN is the complete network of planes, traces, vias, and capacitors that deliver stable power to an IC. A well-designed PDN keeps impedance low across a wide frequency range. It includes bulk capacitors (10 Hz–10 kHz), ceramics (10 kHz–10 MHz), and the PCB planes (>10 MHz).
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Select a capacitor rated at least 1.5–2× the supply voltage to ensure reliable operation and long lifetime. For example, for a 3.3V supply, use a 6.3V or 10V capacitor. Higher ratings reduce performance stress and extend component life.
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No. Bulk capacitors alone cannot respond fast enough to transient currents due to high ESR and ESL. Modern high-speed digital circuits require a multi-layer strategy: bulks for energy storage, ceramics for high-frequency filtering.
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Derating is reducing capacitance to account for voltage applied, temperature, and frequency effects. Ceramic capacitors lose capacitance under DC bias (sometimes 50% or more). Always use actual capacitance under operating conditions, not nameplate value.
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PCB dielectric constant (εr) and loss tangent affect plane capacitance and transmission line behavior. FR-4 is standard but introduces dispersion. For critical high-speed designs, controlled-impedance stackups and low-loss materials improve PDN performance.
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Use this formula: Z = V_ripple ÷ I_transient. For example, if maximum current change is 10 A over 1 ns and tolerable ripple is 100 mV, target PDN impedance is 0.01 Ω. Expensive PDN analysis tools simulate full frequency-domain impedance.